Jail-V: Jailhouse on RISC-V

Complex industrial systems comprise many highly specialised embedded individual components. Especially economic constraints drive the desire to consolidate such components into a stand-alone system. Previous research utilised static hardware partitioning, which can be implemented by exploiting virtualisation extensions of modern CPUs. This offers the possibility to transfer software components from single systems to a consolidated architecture without involved porting efforts.

Unfortunately, restrictions of the target hardware often limit the practical feasibillity of the approach. Novel, open instruction set architectures like RISC-V offer the possibility for efficient hardware/software co-design to address existing architectural deficits. Using synthetisation of processors onto FPGAs, RISC-V offers the possibility to tailor hardware to application scenarios.

The Jail-V project investigates how to design system architectures that are optimally tailored to mixed-criticality, real-time workloads on RISC-V. Specifically, oru work is based on the Jailhouse Hypervisor, whose core has been ported to this emerging architecture as part of the project, jointly with engineers from Siemens Corporate Research.

Using a systematic co-design approach, we create systems that optimally satisfy industrial requirements.


Static Hardware Partitioning on RISC-V - Shortcomings, Limitations, and Prospects
Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer2022.
PDF 10.48550/arXiv.2208.02703 [BibTex]