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Reduction of Virtual Memory Management Overhead: Exploration of Hardware Mechanisms for Second-Level Paging

Embedded hypervisors enable parallel execution of multiple operating systems, by introducing a further abstraction layer between the hardware and the operating systems, that prevents guests from undesired interaction. An aspect of this layer is virtual memory management, where the hypervisor assigns portions of memory to the operating systems and maps these to the physical memory. This technique is called second-level paging and brings additional latencies to memory accesses.

When an application that runs as a guest of the hypervisor accesses the memory, the memory management unit of the CPU may have to resolve the virtual address of the guest and additionally the guest physical address to host physical memory. Removing this overhead in software is not possible, but with modifications to the hardware, the virtualisation overhead could be eliminated.

This thesis aims to quantify address translation overhead and to evaluate the optimisation potential. A modified Open-Source AXI SmartConnect, which is used to build networks between AXI interfaces on hardware, will be developed and integrated between CPU and memory. This SmartConnect can be configured by the CPU to allow or to block certain cores from accessing memory ranges, effectively fulfilling the purpose of the virtual memory management without the additional overhead. Lastly, this thesis will assess whether this approach of allowing an external hardware component to manage memory, a task usually performed by the memory management unit, is a viable solution.