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Tailoring CPUs: Custom modifications of the Rocket-Chip Core in Chisel

Embedded hypervisors enable parallel execution of multiple operating systems on single hardware units. This is achieved by introducing a further abstraction layer between the hardware and the operation systems that prevents guests from undesired interaction with other guests on the platform. One aspect of this layer is virtual memory management, where the hypervisor assigns portions of memory to the operating systems and maps these to the physical memory. This technique is called second-level paging and brings additional latencies to memory accesses.

When an application that runs as a guest of the hypervisor accesses memory, the memory management unit of the CPU may have to resolve the virtual address of the guest and additionally the guest physical address to host physical memory. Removing this overhead in software is not possible, but with modifications to the hardware, the virtualization overhead could be eliminated.

Within the scope of a complementary thesis a modified Open-Source AXI Smart- Connect was developed as a replacement for classical Xilinx AXI components. This component is located between the CPU and memory. This module can be configured to block cores from accessing certain memory ranges, thus acting as virtual memory management without the additional overhead.

This thesis aims to provide the AXI SmartConnect with information of the origin of the request (i.e. core information) to fulfill this functionality. An Open-Source RISC-V CPU, the Rocket-Chip, will be modified to provide information of the core id for external memory accesses. The core id will be channeled to the external SmartConnect of the CPU. This enables the SmartConnect to check if the requested memory address is within the assigned range of the specific cpu core. Lastly, the optimization potential of this mechanism will be evaluated as well as the viability of this solution.