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Systems Architecture and Interface Design for Quantum-Classical Integration

  • Type: Master thesis
  • State: open
  • Projects: SysQC
  • Supervisor: Ralf Ramsauer
  • Student: No Name

We are looking for a motivated student to work on the kernel-level integration of quantum accelerators into classical computing environments. The focus of this project is the definition and implementation of operating system interfaces that enable efficient and low-latency communication between host systems and quantum hardware.

This thesis is within the context of the SysQC project.

Your Tasks:

  • Designing and prototyping kernel-driver interfaces for quantum accelerator cards.
  • Investigating strategies for control flow management: deciding which tasks are executed in the kernel vs. on the accelerator (special-purpose processors).
  • Contributing to the definition of job scheduling, prioritisation, and state handling mechanisms for quantum workloads.
  • Evaluation of different interface strategies with respect to latency, real-time behaviour, and scalability.

Depending on the type (i.e., Bachelor's thesis, Master's thesis or HSP), the scope of tasks is adjusted according to the credit points.

Your Goal:

  • Define and prototype a kernel-to-hardware communication model for quantum accelerators.
  • Explore and evaluate control flow placement (kernel vs. hardware).
  • Provide a performance-oriented assessment of interface designs in simulated or FPGA-based environments.

Your Profile:

  • Interest in the combination of operating systems, system-level architecture, and quantum computing
  • Good handling of the C programming language (mandatory)
  • Good handling of Linux and its command line
  • Basic knowledge in programming of FPGAs (VHDL, Verilog or Chisel, optional)

We offer:

  • Work on a open source software project used in industry
  • Low-level embedded hardware hacking, Linux kernel hacking
  • Boost your own visibility via public contributions to Open Source projects (e.g., Linux, Jailhouse)
  • Work with the emerging RISC-V processor architecture
  • Be part of the team of the Laboratory for Digitalisation
  • Work from home or at the laboratory at the Informatics Building of OTH Regensburg
  • The possibility of further work in our team (Bachelor/Master Theses, HSPs, Research Master)
  • The opportunity for employment at the Laboratory for Digitalisation
  • Free coffee and tea

If you are interested or have further questions just write an email to ralf.ramsauer@oth-regensburg.de

SysQC